Techniques For Handling High Voltage Circuitry In An Integrated Circuit

ABSTRACT

An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

CROSS REFERENCE TO RELATED APPLICATION

This patent application is a continuation of U.S. patent applicationSer. No. 15/294,588, filed Oct. 14, 2016, which is incorporated byreference herein in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates to electrical circuits, and moreparticularly, to techniques for handling high voltage circuitry in anintegrated circuit.

BACKGROUND

A typical programmable integrated circuit may use transistors toimplement programmable switches, which are needed for both programmablelogic and programmable routing structures within the integrated circuit.N-type metal-oxide-semiconductor (NMOS) pass gates may be used toimplement the programmable switches in some cases, while in other cases,static complementary metal oxide semiconductor (CMOS) pass gates withboth NMOS and P-type metal-oxide-semiconductor (PMOS) transistors may beused to implement the programmable switches. For either one of thesecases, voltage reliability requirements may prevent too high a voltagefrom being applied across any two ports of the NMOS or PMOS transistors.

Instead of using NMOS or PMOS transistors for the programmablestructures, alternative switch structures are continually beingevaluated for use within a programmable integrated circuit. Thealternative switch structures are generally non-volatile, which meansthat the switch structures do not lose programming state when the powersupply is powered down. But in order to program these non-volatilealternative switch structures, a higher voltage is typically needed tofacilitate the switch programming. The need for the switches to maintaintheir programmed operations during normal mode of operation (i.e.,without getting accidentally reprogrammed) implies that the programmingvoltage must be at a higher voltage than the normal logic operatingvoltage of the integrated circuit. However, the problem of overdrivingother circuit elements such as logic circuits may arise when providingthe higher voltage to the switch structures. Such a problem may causedevice reliability issues and subsequently lead to device failure.

SUMMARY

The present invention provides techniques for handling high voltagecircuitry in an integrated circuit.

The present invention can be implemented in numerous ways, such as aprocess, an apparatus, a system, or a device. Several embodiments of thepresent invention are described below.

An integrated circuit formed using a semiconductor substrate isdisclosed. The integrated circuit includes a logic circuit and a switchcircuit. The logic circuit operates at a first power supply voltage andthe switch circuit operates at a second power supply voltage that isgreater than the first power supply voltage. The logic circuit is formedwithin a first triple well structure within the semiconductor substratethat is supplied with a first bias voltage. The switch circuit is formedwithin a second triple well structure that is electrically isolated fromthe first triple well structure within the semiconductor substrate andis supplied with a second bias voltage. The switch circuit receives acontrol signal that controls the first bias voltage during a programmingoperation of the integrated circuit.

Another integrated circuit is disclosed. The integrated circuit includesa logic circuit that operates in a first power supply domain and aswitch circuit that operates in a second power supply domain that isdifferent than the first power supply domain. The logic circuit receivesa first bias signal on a first signal path. The switch circuit receivesa second bias signal on a second path that is different than the firstsignal path and a control signal that controls a voltage of the firstbias signal to turn off a transistor in the logic circuit during aprogramming operation of the integrated circuit.

A method of operating an integrated circuit is disclosed. The methodincludes receiving a first bias signal using a logic circuit through afirst signal path and a second bias signal using a switch circuitthrough a second signal path that is different than the first signalpath. The logic circuit operates in a first power supply voltage and theswitch circuit operates in a second power supply voltage that is higherthan the first power supply voltage. The method further includescontrolling a voltage of the first bias signal to the logic circuit inresponse to a control signal to turn off a transistor in the logiccircuit during a programming operation of the integrated circuit. Forexample, the voltage of the first bias signal is adjusted relative tothe first power supply voltage or a voltage of the second bias signalbased on a logic state of the control signal.

Further features of the invention, its nature, and various advantages,will be more apparent from the accompanying drawings and the followingdetailed description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an illustrative integrated circuit inaccordance with an embodiment of the present invention.

FIG. 2 shows a structure of an illustrative integrated circuit formed ina semiconductor substrate in accordance with an embodiment of thepresent invention.

FIGS. 3A and 3B are corresponding circuit diagrams of the illustrativeintegrated circuit of FIG. 2 in accordance with one embodiment of thepresent invention.

FIG. 4 is a timing diagram illustrating the behavior of signals duringoperation of an integrated circuit in accordance with one embodiment ofthe present invention.

FIG. 5 shows another structure of an illustrative integrated circuithaving a switch circuit, an isolation circuit, and a logic circuitformed in a semiconductor substrate in accordance with an embodiment ofthe present invention.

FIG. 6 is a corresponding circuit diagram of the illustrative integratedcircuit of FIG. 5 in accordance with one embodiment of the presentinvention.

FIG. 7 is a flow chart of illustrative steps for operating an integratedcircuit in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

The embodiments provided herein include techniques for handling highvoltage circuitry for an integrated circuit.

FIG. 1 is a diagram of an illustrative integrated circuit 10 inaccordance with an embodiment of the present invention. Integratedcircuit 10 has input-output (IO) circuitry 12 for driving signals off ofintegrated circuit 10 and for receiving signals from other circuits ordevices via IO pins 14. Interconnection resources 16 such as global andlocal vertical and horizontal conductive lines and busses may be used toroute signals on integrated circuit 10. Interconnection resources 16include fixed interconnects (conductive lines) and programmableinterconnects (e.g., programmable connections between respective fixedinterconnects). The programmable interconnects associated withinterconnection resources 16 may be considered to be a part ofprogrammable logic regions 18.

Memory elements 20 may be formed using complementarymetal-oxide-semiconductor (CMOS) integrated circuit technology (as anexample). In the context of a programmable logic device, memory elements20 may store configuration data and are therefore sometimes referred toas configuration random-access memory (CRAM) cells. In general,configuration random-access memory elements 20 may be arranged in anarray pattern. In a programmable integrated circuit, there may bemillions of memory elements 20 on a single device. A user (e.g., a logicdesigner) may provide configuration data for the array of memoryelements during programming operation. Once loaded with configurationdata, memory elements 20 may selectively control (e.g., turn on and off)portions of the circuitry in programmable logic regions 18 and therebycustomize its functions as desired.

Horizontal and vertical conductors and associated control circuitry maybe used to access memory elements 20 when memory elements 20 arearranged in an array. The control circuitry, for example, may be used toclear all or some of the memory elements. The control circuitry may alsowrite data to memory elements 20 and may read data from memory elements20. Memory elements 20 may be loaded with configuration data, forinstance, in CRAM arrays. The loaded configuration data may then be readout from the memory array to confirm proper data capture beforeintegrated circuit 10 is used during normal operation in a system.

The circuitry of integrated circuit 10 may be organized using anysuitable architecture. For example, programmable logic regions 18 may beorganized in a series of rows and columns of larger programmable logicregions each of which contains multiple smaller regions. The largerregions are sometimes referred to as logic array blocks. The smallerlogic regions are sometimes referred to as logic elements. A typicallogic element may contain a look-up table, registers, and programmablemultiplexers. If desired, programmable logic regions 18 may be arrangedin more levels or layers in which multiple large regions areinterconnected to form still larger portions of logic.

In addition to the relatively large blocks of programmable logic regions18 that are shown in FIG. 1, integrated circuit 10 generally alsoincludes some programmable logic components associated with IO circuitry12 on integrated circuit 10. For example, IO circuitry 12 may includeswitch circuits (or switches). The switch circuits may allow flexibleand scalable cross connections between various components in theprogrammable logic regions 18 on integrated circuit 10. The switchcircuits may also allow communication between selected inputs andoutputs for programmable logic regions 18 to interconnection resources16 or IO circuitry 12 to and from components on the integrated circuitor devices external to the integrated circuit. Programming the switchcircuits typically requires high voltage to be supplied in order tomaintain the programmed operations of the switch circuits during thenormal mode of operation. However, this may result in overdrivinglow-voltage logic circuits within programmable logic regions 18 whenproviding the high voltage to the switch circuits during a switchprogramming operation. Such a problem may cause device reliabilityissues and subsequently damage the integrated circuit.

To solve this problem, an efficient high voltage handling mechanism isrequired to ensure that no voltage-sensitive devices will be subjectedto high voltage, and that no significant current contention will occurduring power supply transitions during the switch programming operation.Such a mechanism, which will be described in detail below, mayelectrically isolate the high-voltage switch circuits fromvoltage-sensitive circuit elements (e.g., logic circuits) withinintegrated circuit 10. Such a mechanism may also provide the ability toadjust power supply voltage levels to enable switch circuits to bepowered at a higher voltage without causing any contention problems withother low-voltage circuit elements.

FIG. 2 shows a structure of an illustrative integrated circuit 200formed in semiconductor substrate 206 in accordance with an embodimentof the present invention. Integrated circuit 200 includes switch circuit202 and logic circuit 204. Switch circuit 202 may include threetransistors (e.g., P-type metal-oxide-semiconductor (PMOS) transistors220 and 222, and N-type metal-oxide-semiconductor (NMOS) transistor224), which are implemented as thick oxide devices. Accordingly, logiccircuit 204 may include three transistors (e.g., PMOS transistors 230and 232, and NMOS transistor 234), which are implemented as thin-oxidedevices. That is, a layer of oxide material that is formed underneatheach of gate stacks 214 (or polysilicon gates 214) of transistors 220,222, and 224 is thicker than a corresponding layer of oxide material ineach of gate stacks 215 (or polysilicon gates 215) of transistors 230,232, and 234.

Thick-oxide devices are generally ideal for sustaining high voltage ininterface circuitry such as switch circuit 202, and thin-oxide devicesare preferred for sustaining high speed and lower power consumption indigital core circuitry such as logic circuit 204. In one embodiment,switch circuit 202 and logic circuit 204 may operate at differentvoltage levels to accommodate transfer of signals from a higher supplyvoltage to a lower supply voltage, and vice versa. For example, switchcircuit 202 and logic circuit 204 may be supplied with a lower powersupply voltage (e.g., positive power supply voltage level VCCL) fornormal signal transmission operation (i.e., during a user mode). When aprogramming mode is activated on integrated circuit 200, switch circuit202 may be supplied with a higher operating voltage (e.g., positivepower supply voltage level VCCH) to facilitate a switch programmingoperation (i.e., selectively switch programming data between adjacentcolumns of logic regions (e.g., programmable logic regions 18 of FIG. 1)in integrated circuit 200). However, the higher voltage may potentiallyoverdrive logic circuit 204 and damage or destroy the internal circuitryof integrated circuit 200.

To prevent the overdriving problem, a triple well process can be used toprovide electrical isolation between switch circuit 202 and logiccircuit 204. In an exemplary embodiment shown in FIG. 2, switch circuit202 and logic circuit 204 may be formed using the triple well process insubstrate 206. Substrate 206 is a positively doped (P-type) substratethat is connected to ground (e.g., VSS) of integrated circuit 200.Hence, substrate 206 may also be referred to as P-type substrate 206. Inswitch circuit 202, NMOS transistor 224 is formed within an isolatedP-type well (positively doped region, e.g., R-Well 210A), within largerN-wells 212A and 213A, which in turn reside within P-type substrate 206.PMOS transistors 220 and 222 are formed within the respective N-wells212A and 213A, which also reside within P-type substrate 206. Similarly,in logic circuit 204, NMOS transistor 234 is formed within R-Well 210B,within larger N-wells 212B and 213B, which in turn reside within P-typesubstrate 206. PMOS transistors 230 and 232 of logic circuit 204 areformed within the respective N-wells 212B and 213B, which also residewithin P-type substrate 206. Each of switch circuit 202 and logiccircuit 204 is formed in a separate deep N-well (e.g., deep N-wells 208Aand 208B), which electrically isolates switch circuit 202 and logiccircuit 204 from each other and from P-type substrate 206.

Accordingly, separate power supply voltage rails, known as biasvoltages, can be provided externally or internally for both switchcircuit 202 and logic circuit 204. A bias voltage of power supplyvoltage source VSS (also referred to as bias voltage VSS herein) may beapplied to a region (e.g., N+ region) of R-well 210A of switch circuit202, and another bias voltage of a power supply voltage source (alsoreferred to as bias voltage VSS_I herein) may be applied to a region(e.g., N+region) of R-well 210B of logic circuit 204. In an embodimentof the present invention, back bias voltage VSS_I can be dynamicallyadjusted to provide different biases to turn off the transistors 230,232, and 234 in logic circuit 204 to cut off a conductive path betweenswitch circuit 202 and logic circuit 204. This is to avoid overdrivinglogic circuit 204 during a high-voltage switch programming operation. Amore detailed description on how VSS_I can be modified will be describedbelow.

FIGS. 3A and 3B are corresponding circuit diagrams of the illustrativeintegrated circuit 200 of FIG. 2 in accordance with one embodiment ofthe present invention. As described above, integrated circuit 200includes switch circuit 202 and logic circuit 204. Positive power supplyvoltages VCCH or VCCL may be provided to switch circuit 202. Positivepower supply voltage VCCL may be provided to logic circuit 204. Groundvoltage VSS may be provided from an external source to switch circuit202 and logic circuit 204. As shown in FIG. 3A, switch circuit 202 mayinclude three inverter driver circuits 302A, 302B, and 302C and logiccircuit 204 may include three inverter driver circuits 304A, 304B, and304C, and two NAND gates 306A and 306B. Inverter driver circuits 302A,302B, and 304A may collectively be referred to as internal circuit 303.In one embodiment, internal circuit 303 enables the internal driving ofinput signals of switch circuit 202 and logic circuit 204.

As described above in FIG. 2, the use of triple well isolation inintegrated circuit 200 allows logic circuit 204 to be biased separatelyfrom switch circuit 202 and P-type substrate 206 of FIG. 2. For example,as shown in FIG. 3, switch circuit 202 may receive a bias signal VSS andits corresponding bias voltage (collectively referred to as VSS herein)through signal path 320, and logic circuit 204 may receive another biassignal VSS_I and its corresponding bias voltage (collectively referredto as VSS_I herein) through signal path 322 that is different thansignal path 320. Such a configuration enables VSS_I to be controlled,which will be described in an example below, to provide high voltagehandling within integrated circuit 200 during the switch programmingoperation.

Referring to FIG. 3A, assume that logic circuit 204 can handle a maximumoperating voltage of 1 volt (VCCL), across its transistor ports, andswitch circuit 202 can operate with low voltages (VCCL) or high voltages(VCCH), depending on which mode the integrated circuit 200 operates. Forexample, in an embodiment of FIG. 3A, switch circuit 202 may have avoltage requirement of 1 volt, in which switch circuit 202 operates likea normal (logic) circuit during the user mode of integrated circuit 200.Alternatively, in another embodiment of FIG. 3B, switch circuit 202 mayhave a voltage requirement of 2 volts to facilitate the switchprogramming operation during the programming mode of the integratedcircuit. It should be noted that a VSS of 0 volts may be used torepresent a low logic level (a “0”) and a VCCL of 1 volt may be used torepresent a high logic level (a “1”) in the following description.

When the programming mode is activated on integrated circuit 200, theinput signals of switch circuit 202 may be driven to high voltage (e.g.,VCCH) to facilitate the high-voltage switch programming operation. Itshould be appreciated that the circuit configuration of switch circuit202 of FIG. 3B may be used to facilitate the switch programmingoperation. In this mode, control signal 301 is first applied to inverterdriver circuit 335. An inverted version of control signal 301 is thenapplied to internal circuit 303, causing internal circuit 303 togenerate (via inverter driver circuit 302A) a switch control signal ENPBof logic level “0” and its inverted signal ENP of logic level “1”. TheENPB signal is provided to logic circuit 204 to set logic circuit 204 ata “don't care” state, which means that no matter what input signal(e.g., input signal 324) is applied to logic circuit 204 (through NANDgate 306A), the input signal will have no effect on the output of logiccircuit 204, because the output signals of NAND gates 306A and 306B eachremain at a logic level “1” in response to the ENPB signal being a logiclevel “0.” Also, buffer circuit 360 is tri-stated (i.e., put into a highimpedance state) in response to the ENPB signal being a logic level “0”and the ENP signal being at a logic high level “1.” Such a configurationensures that the output of logic circuit 204 can be driven out (throughNAND gate 306B) at its nominal operating voltage (i.e., VCCL) prior tothe switch programming operation.

Accordingly, VSS_I is adjusted relative to VCCL when the ENPB signal isasserted at logic level “0”. As VSS_I is ramped towards VCCL, the output(e.g., output 326) of logic circuit 204 will be driven to a highimpedance state, and VCCH can be increased (i.e. from 1 volt to 2 volts)accordingly for the switch programming operation. In this scenario,driver circuit 340 of switch circuit 202, which is controlled by the ENPsignal, may be able to output high-voltage switch-programming logicinput signals (e.g., input signals 324) to facilitate the switchprogramming operation. In one embodiment, logic circuit 204 may bedisabled (or deactivated) from operating during the switch programmingoperation. Alternatively, in another embodiment, logic circuit 204 mayact as an isolation circuit and isolate other logic circuits (not shown)from switch circuit 202 during the switch programming operation. Foreither one of the embodiments, the above configuration enables switchcircuit 202 to drive the high-voltage input signals directly to programthe integrated circuit 200 without causing current contention with thelogic circuit(s).

Once the switch programming operation is completed, VCCH is lowered toVCCL, and switch circuit 202 will be able to drive its input signals toVCCL through internal circuit 303. In this scenario, VSS_I is adjustedrelative to VSS, and thus enabling logic circuit 204 to drive itssignals at VCCL. Such a configuration will not cause contention, becauseboth switch circuit 202 and logic circuit 204 will be driving theirsignals to the same voltage levels (i.e., VCCL). Subsequently, the ENPBsignal is de-asserted at logic level “1” to allow normal inter-blocksignals to operate normally in the user mode. With proper transitioningof power supply voltages and interface signals, it can be ensured thatno thin-oxide devices such as in logic circuit 204 will be subjected tohigh voltage, and that no significant current contention will occurduring the transitions of the power supply voltage due to a changebetween the two operating modes of integrated circuit 200.

FIG. 4 is a timing diagram 400 illustrating the behavior of relevantsignals in the circuitry of FIGS. 2 and 3 in accordance with oneembodiment of the present invention. It should be appreciated that theembodiments of FIGS. 2 and 3 may be used as examples to describe thetiming diagram 400. As shown, timing diagram 400 illustrates thepositive power supply voltage of switch circuit 202 (e.g., VCCH),positive power supply voltage signal of logic circuit 204 (e.g., VCCL),bias signal VSS of switch circuit 202, bias signal VSS_I of logiccircuit 204, switch control signal ENPB (or ENPB signal), and aninverted version of switch control signal ENPB (i.e., ENP signal).

In an example described above with respect to FIG. 3A, assume that logiccircuit 204 can handle a maximum operating voltage of 1 volts (e.g.,VCCL) across its transistor ports, and switch circuit 202 has anoperating voltage requirement of 2 volts (e.g., VCCH) to facilitate thehigh-voltage switch programming operation. When integrated circuit 200is powered on, integrated circuit 200 may operate in normal operatingmode (or user mode).

In this mode, integrated circuit 200 is supplied with a source ofcurrent at a normal operating voltage level (e.g., VCCL) to be poweredon.

At time T₁, the ENPB signal is asserted low (i.e., driven to VSS orlogic “0” value) and an inverted version of ENPB (i.e., the ENP signal)is provided at logic “1” to trigger the switch programming operationwithin integrated circuit 200. As described above, a voltage that ishigher than VCCL is typically needed to facilitate the switchprogramming operation. Hence, when switch programming operation is beingdone, the ENPB signal is driven to VSS to ensure that logic circuit 204is at a “don't care” state from a contention standpoint, which meansthat any input signal that is applied to logic circuit 204 from switchcircuit 202 will not have any effect on the output of logic circuit 204.Such a configuration ensures that the output of logic circuit 204 isdriven out at its nominal operating voltage (i.e., VCCL) prior to theswitch programming operation, which may then allow switch circuit 202 todrive its input internally and in parallel at VCCL.

At time T₂, VSS_I is ramped towards VCCL. Accordingly, VCCH is rampedtowards a predetermined voltage at time T₃. During the time intervalbetween T₂ and T₃, logic circuit 204 will be tri-stated (i.e., put intoa high impedance state), causing the output (e.g., output 326) of logiccircuit 204 to be driven out at high impedance. As a result, switchcircuit 202 is able to drive the high-voltage switch-programming logicinput signals (e.g., input signals 324) directly at the predeterminedvoltage (e.g., using driver circuit 340 of FIG. 3B) between times T₃ andT₄ to program the integrated circuit without affecting the normaloperation of logic circuit 204. The predetermined voltage is higher thanthe normal operation voltage of the integrated circuit. Thepredetermined voltage may be a high voltage of, for example, 2 volts.

After the completion of the switch programming operation, switch circuit202 will drive its input signals 324 to VCCL through internal circuit303 of FIG. 3A. In this scenario, VCCH is lowered from the predeterminedvoltage level (i.e., 2 volts) and returned to the normal operationvoltage (i.e., VCCL of 1 volt) at time T₄. Accordingly, at time T₅,VSS_I is lowered from VCCL to VSS to save static power and also toprevent overdriving the circuit elements in the integrated circuit. OnceVSS_I is fully ramped to 0 volt, the ENPB and ENP signals can then berespectively de-asserted high (i.e., driven to VCCL or logic “1”) andlow (i.e., logic “0”) at time T₆. This allows the normal interblocksignals to operate normally in the user mode. Subsequently, logiccircuit 204 will start driving signals at VCCL without causing anycontention issue since the signals are driving to the same VCCL levels.

In the case when a logic circuit is disabled from operating during theswitch programming operation, an intermediate triple well arrangementthat includes a thin-oxide isolation circuit can be used to allow thelogic circuit to remain logically operational during the switchprogramming operation. FIG. 5 shows a structure of an illustrativeintegrated circuit 500 having switch circuit 502, isolation circuit 503,and logic circuit 504 formed in semiconductor substrate 206 inaccordance with one embodiment of the present invention. Positive powersupply voltages VCCH or VCCL may be provided to switch circuit 502.Positive power supply voltage VCCL may be provided to isolation circuit503 and logic circuit 504. Ground voltage VSS may be provided from anexternal source to switch circuit 502 and logic circuit 504. It shouldbe noted that integrated circuit 500 may be formed in a similar process(i.e., triple well process) as integrated circuit 200 of FIG. 2 (e.g.,switch circuit 202 and logic circuit 204). As such, for the sake ofbrevity, the similar components (e.g., P-well 510A, P-well 520A, P-well520B, N-well 512A, N-well 513A, N-well 522A, N-well 523A, N-well 522B,N-well 523B, deep N-well 508A, deep N-well 528A, deep N-well 528B, andP-type substrate 206) that collectively form a group of transistorswithin respective switch circuit 502, isolation circuit 503, and logiccircuit 504 will not be described in detail.

In order to enable logic circuit 504 to remain logically operationalduring the switch programming operation, isolation circuit 503 isimplemented to isolate high voltage nodes from switch circuit 502 fromlow voltage nodes from logic circuit 504. The use of triple wellisolation in integrated circuit 500 allows isolation circuit 503 to bebiased separately from switch circuit 502, logic circuit 504, and P-typesubstrate 206. For example, as shown in FIG. 5, switch circuit 502 andlogic circuit 504 may be supplied with a bias signal and voltage VSS,and isolation circuit 503 may be supplied with another bias signal andbias voltage VSS_I. Isolation circuit 503 is connected to an isolatedP-well (e.g., R-well 520A) so that the supplied VSS_I can be modified.Such a configuration creates an ability for isolation circuit 503 todrive signals between switch circuit 502 and logic circuit 504 withoutcausing current contention. As such, logic circuit 504 is able to staylogically operational during the switch programming operation.

FIG. 6 is a corresponding circuit diagram of the illustrative integratedcircuit 500 of FIG. 5 in accordance with one embodiment of the presentinvention. As described above, integrated circuit 500 includes switchcircuit 502, isolation circuit 503, and logic circuit 504. Switchcircuit 502 may be substantially similar to switch circuit 202 of FIGS.3A and 3B and thus, similar circuit elements (e.g., inverter drivercircuits 302A, 302B, 302C, and 302D, driver circuit 340, and buffercircuit 360) are not shown or described again for the sake of brevity.Inverter driver circuits 302A and 302B may be collectively referred toas internal circuit 603. In one embodiment, internal circuit 603 enablesthe internal driving of input signals of switch circuit 502. Isolationcircuit 503 may include tri-state NAND gate 602 and tri-state invertercircuit 604. Logic circuit 504 may include tri-state inverter circuit605 and NOR gate 606.

When the programming mode is activated on integrated circuit 500, theinput signals of switch circuit 502 may be driven to high voltage (e.g.,VCCH) to facilitate the high-voltage switch programming operation. Itshould be appreciated that the circuit configuration of switch circuit202 of FIG. 3B may be used by switch circuit 502 to facilitate theswitch programming operation. In this mode, control signal 301 is firstapplied to inverter driver circuit 335, which is shown in FIG. 3B. Aninverted version of control signal 301 is then applied to internalcircuit 603, causing internal circuit 603 to generate (via inverterdriver circuit 302A) a switch control signal ENPB of logic level “0” andits inverted signal ENP of logic level “1”. The ENPB signal is providedto logic circuit 504 through isolation circuit 503 to set logic circuit504 at a “don't care” state, which means that no matter what input(e.g., control signal 301) is applied to logic circuit 504, the inputwill have no effect on the output of logic circuit 504, because theoutput signal of NAND gate circuit 602 remains a logic level “1” inresponse to the ENPB signal being a logic level “0.” Such aconfiguration ensures that the output of logic circuit 504 can be drivenout (through NOR gate 606) at its nominal operating voltage (i.e., VCCL)prior to the switch programming operation.

Accordingly, VSS_I is adjusted relative to VCCL when the ENPB signal isasserted at logic level “0”. As VSS_I is ramped towards VCCL, isolationcircuit 503 is tri-stated (i.e., put into a high impedance state) andfunctions to isolate logic circuit 504 from switch circuit 502 duringthe switch programming operation. As such, VCCH can be increased (i.e.from 1 volt to 2 volts) accordingly, and switch circuit 502 will be ableto drive the high-voltage logic signals (i.e., switch-programming logicsignals) directly (i.e., using driver circuit 340 and buffer circuit 360of FIG. 3B) to program integrated circuit 500 without causing currentcontention with logic circuit 504. Accordingly, logic circuit 504 isable to remain operational without being subjected to high voltageduring the switch programming operation.

Once the switch programming operation is completed, VCCH is lowered toVCCL, and switch circuit 502 will be able to drive its input signals toVCCL through internal circuit 603. Accordingly, VSS_I is adjustedrelative to VSS. In this scenario, isolation circuit 503 may functionlike a corresponding normal (non-tri-state) circuit and “de-isolate”switch circuit 502 from logic circuit 504. Subsequently, the ENPB signalis de-asserted at logic level “1” to allow normal inter-block signals tooperate normally between switch circuit 502 and logic circuit 504 in theuser mode.

FIG. 7 is a flow chart of illustrative steps for operating an integratedcircuit in accordance with one embodiment of the present invention. Itshould be appreciated that the embodiments of FIGS. 2, 3A, 3B, 5, and 6may be used as examples implemented by the steps described below.

At step 700, a first bias signal and a first bias voltage are receivedusing a logic circuit of the integrated circuit on a first signal path,where the logic circuit operates at a first power supply voltage. Forexample, as shown in FIGS. 2, 3A, and 3B, bias signal and bias voltageVSS_I are received using logic circuit 204 of integrated circuit 200 onsignal path 322, where logic circuit 204 operates at power supplyvoltage VCCL. In another example, as shown in FIGS. 5 and 6, bias signaland bias voltage VSS_I are received using isolation circuit 503 ofintegrated circuit 500, where isolation circuit 503 operates at powersupply voltage VCCL. In one embodiment, isolation circuit 503 may be alogic circuit that is configured to provide isolation between switchcircuit 502 and logic circuit 504 of FIGS. 5 and 6.

At step 702, a second bias signal and a second bias voltage are receivedusing a switch circuit of the integrated circuit on a second signalpath, where the switch circuit operates at a second power supplyvoltage. For example, as shown in FIGS. 2, 3A, and 3B, bias signal andbias voltage VSS are received using switch circuit 202 of integratedcircuit 200 on signal path 320, where switch circuit 202 operates atpower supply voltage VCCH or power supply voltage VCCL, depending on theoperation mode of the integrated circuit. In another example, as shownin FIGS. 5 and 6, VSS is received using switch circuit 502 and logiccircuit 504.

When the integrated circuit is powered on, the integrated circuitoperates in a normal user mode at step 704. For example, referring toFIGS. 2, 3A, 3B, 5, and 6, integrated circuits 200 and 500 may besupplied with VCCL to be powered on. In this scenario, the powered-onintegrated circuits may operate in the normal mode of operation (i.e.,user mode) after being initialized in a predetermined manner upon theactivation of the powered-on integrated circuit.

In one embodiment, the logic circuit is responsive to a switch controlsignal (e.g., ENPB signal of FIGS. 2, 3, 5, and 6) having two logicstates (e.g., logic “1” or logic “0”) indicative of the two operatingmodes on the integrated circuit. The switch control signal is generatedby the switch circuit as part of a voltage handling mechanism to protectthe logic circuit from excessive voltages during the switch programmingoperation. For example, as shown in FIG. 3B, when the programming modeis activated on the integrated circuit, a control signal (e.g., controlsignal 301) is first applied to the internal circuit (e.g., internalcircuit 303 of FIGS. 3A and 3B) of the switch circuit (e.g., switchcircuit 202 of FIG. 3B), causing the internal circuit to generate theswitch control signal at the first logic state (e.g., logic “1” or 1V).In this mode, the first bias voltage VSS_I (e.g., VSS_I of FIGS. 2, 3A,3B, 5 and 6), and the second power supply voltage (e.g., VCCH) may beadjusted to enable the switch circuit to be powered at a higher voltagewithout causing any contention problems with other low-power logiccircuits.

For example, as shown in FIG. 3B, if the switch control signal ENPB isasserted at step 705, VSS_I is adjusted relative to the first powersupply voltage VCCL at step 706 so that transistors 230, 232, and 234 oflogic circuit 204 can be turned off to cut off a conductive path betweenswitch circuit 202 and logic circuit 204. For example, VSS_I may beincreased to equal VCCL (e.g., as shown between T₂ and T₅ in FIG. 4) instep 706 so that there is no voltage drop across transistors 230, 232,and 234. This is to prevent logic circuit 204 from being subjected toexcessive voltage during the switch programming operation. Accordingly,the second power supply voltage that is supplied to the switch circuitis adjusted relative to a predetermined voltage at step 708. In oneembodiment, the predetermined voltage is applied to the switch circuitto enable the switch programming operation on the integrated circuit.The predetermined voltage may be higher than the normal operationvoltage of the integrated circuit. The predetermined voltage may be ahigh voltage of, for example, 2 volts. As such, the switch circuit ispowered at a higher voltage without causing any contention problems withother low-voltage circuit elements.

Such a configuration allows the switch programming operation to beperformed at the adjusted second power supply voltage using the switchcircuit at step 710. Once the switch programming operation is completed,the switch control signals (i.e., ENP and ENPB signals), the first biasvoltage VSS_I, and power supply voltage VCCH are reset to their originalconfiguration states in the user mode at step 712.

The present exemplary embodiments may be practiced without some or allof these specific details described with reference to the respectiveembodiments. In other instances, well-known operations have not beendescribed in detail in order not to obscure unnecessarily the presentembodiments.

The methods and apparatuses described herein may be incorporated intoany suitable circuit. For example, the methods and apparatuses may beincorporated into numerous types of devices such as microprocessors orother integrated circuits. Exemplary integrated circuits includeprogrammable array logic (PAL), programmable logic arrays (PLAs), fieldprogrammable logic arrays (FPGAs), electrically programmable logicdevices (EPLDs), electrically erasable programmable logic devices(EEPLDs), logic cell arrays (LCAs), field programmable gate arrays(FPGAs), application specific standard products (ASSPs), applicationspecific integrated circuits (ASICs), and microprocessors, just to namea few.

Although the method operations were described in a specific order, itshould be understood that other operations may be performed in betweendescribed operations, described operations may be adjusted so that theyoccur at slightly different times or described operations may bedistributed in a system which allows the occurrence of the processingoperations at various intervals associated with the processing, as longas the processing of the overlay operations are performed in a desiredway.

What is claimed is:
 1. An integrated circuit comprising: a switchcircuit comprising a first transistor coupled to receive a first supplyvoltage; and a logic circuit comprising a second transistor coupled toreceive a second supply voltage and a first bias signal, wherein thefirst bias signal is increased to the second supply voltage causing thesecond transistor to turn off and thereby cutting off a conductive pathbetween the switch circuit and the logic circuit, and wherein the firstsupply voltage is increased to a predetermined voltage that is appliedto the first transistor to enable the switch circuit to drive an inputsignal at the predetermined voltage while the second transistor is off.2. The integrated circuit of claim 1, wherein the predetermined voltageis greater than the second supply voltage.
 3. The integrated circuit ofclaim 1, wherein the switch circuit is coupled to receive a second biassignal that is at a ground voltage, and wherein the first bias signal isincreased from the ground voltage to the second supply voltage.
 4. Theintegrated circuit of claim 1, wherein the logic circuit is an isolationcircuit that isolates high voltage nodes in the switch circuit from lowvoltage nodes in an additional logic circuit in the integrated circuit.5. The integrated circuit of claim 1, wherein the first bias signal isdecreased to a ground voltage after a switch programming operationcausing the second transistor to turn on.
 6. The integrated circuit ofclaim 1, wherein the switch circuit drives the input signal at thepredetermined voltage during a switch programming operation to programthe integrated circuit without affecting normal operation of the logiccircuit.
 7. The integrated circuit of claim 1 further comprising: asemiconductor substrate, wherein the switch circuit is electricallyisolated from the logic circuit within the semiconductor substrate. 8.The integrated circuit of claim 7, wherein the logic circuit is in afirst triple well structure within the semiconductor substrate, andwherein the switch circuit is in a second triple well structure withinthe semiconductor substrate that is electrically isolated from the firsttriple well structure.
 9. A method for programming an integratedcircuit, the method comprising: providing a first supply voltage to afirst transistor in a switch circuit; providing a second supply voltageand a first bias signal to a second transistor in a logic circuit;turning off the second transistor to cut off a conductive path betweenthe switch circuit and the logic circuit in response to the first biassignal increasing to the second supply voltage; and increasing the firstsupply voltage to a predetermined voltage that is applied to the firsttransistor to enable the switch circuit to drive an input signal at thepredetermined voltage while the second transistor is off.
 10. The methodof claim 9 further comprising: providing a second bias signal that is ata ground voltage to the switch circuit, wherein the first bias signal isincreased from the ground voltage to the second supply voltage.
 11. Themethod of claim 9 further comprising: driving the input signal at thepredetermined voltage with the switch circuit during a switchprogramming operation to program the integrated circuit withoutaffecting a normal operation of the logic circuit.
 12. The method ofclaim 9 further comprising: decreasing the first bias signal to a groundvoltage after a switch programming operation causing the secondtransistor to turn on.
 13. The method of claim 9, wherein increasing thefirst supply voltage to the predetermined voltage further comprisesincreasing the first supply voltage to the predetermined voltage that isgreater than the second supply voltage.
 14. The method of claim 9,wherein the logic circuit is in a first triple well structure within asemiconductor substrate, and wherein the switch circuit is in a secondtriple well structure within the semiconductor substrate that iselectrically isolated from the first triple well structure.
 15. Anintegrated circuit comprising: a switch circuit comprising a firstdriver circuit, wherein the switch circuit is coupled to receive a firstsupply voltage and a first bias signal of a first power supply voltagesource; and a logic circuit coupled to receive a second supply voltageand a second bias signal of a second power supply voltage source,wherein the first supply voltage is increased to a predetermined voltageand the second bias signal is increased from a voltage of the first biassignal to the second supply voltage for a switch programming operation,and wherein the first driver circuit outputs a switch programming logicsignal at the predetermined voltage in response to a switch controlsignal during the switch programming operation.
 16. The integratedcircuit of claim 15, wherein the switch circuit further comprises asecond driver circuit, wherein the logic circuit comprises a first logicgate circuit, and wherein the second driver circuit is coupled toprovide the switch control signal to the first logic gate circuit toprevent an input signal to the logic circuit from having an effect on anoutput signal of the logic circuit during the switch programmingoperation.
 17. The integrated circuit of claim 16, wherein the logiccircuit further comprises a second logic gate circuit, and wherein anoutput of the second logic gate circuit is driven to a high impedancestate in response to the second bias signal being increased to thesecond supply voltage.
 18. The integrated circuit of claim 15, whereinthe predetermined voltage is greater than a normal operation voltage ofthe integrated circuit.
 19. The integrated circuit of claim 15, whereinthe logic circuit acts as an isolation circuit that isolates other logiccircuits from the switch circuit during the switch programmingoperation.
 20. The integrated circuit of claim 15 further comprising: asemiconductor substrate, wherein the switch circuit is electricallyisolated from the logic circuit within the semiconductor substrate. 21.The integrated circuit of claim 15, wherein the logic circuit isdisabled from operating during the switch programming operation.